When switching a large high voltage power FET gate that has hundreds of pF gate capacitances, depending on the process technology the gate maximum voltage rating will be limited to a much lower level than the high voltage supply (VDH). To effectively drive its switching, conventional systems tend to use systematically a well-decoupled supply where an external capacitor is often needed.
An example of a prior art large high voltage power FET gate driving circuit 700 is illustrated in a circuit schematic block diagram in FIG. 7. The circuit 700 includes the high voltage power FET 750 and the gate driving circuit 710. The driving output 736 from the gate driving circuit 710 is coupled to the gate 772 of the power FET SW1 to charge the gate capacitance.
The power FET SW1 is powered by the high voltage 778. Its gate capacitance Cg is of several hundred pF (for example, 400 pF). The voltage regulator VREG is coupled to the high voltage rail (VDH) 784 as the charging source, and is coupled to the driver B1 at 722. An external capacitance CEXT and an external inductance LEXT are coupled between GND and 722. The switching signal IN is coupled to the input 712 of the driver B1.
For an RC type charging shown in FIG. 7, if the equivalent gate capacitance is 400 pF with 6 Ohm pull up for a target 5 ns rise time through just 1 nH of supply parasitic inductance, in FIG. 8 shows the resultant gate voltage charging curve 812, the charging current curve 832, and the low voltage supply (VDL) curve 842. It is apparent that when the gate voltage is charged with a voltage swing 3.21 V within 5.016 S, the charging current 832 has a peak up to close 600 mA. Most significantly, the low voltage supply (VDL) 842 has a sharp drop from 4.0 V to 1.25 V mainly due to the peak charging current rise in ˜100 ps. When the same VDL supply 722 in FIG. 7 is shared among other analog functions, either continuous or switching, such perturbation will not be acceptable.
One way to mitigate this high level noise is to use a passive local low pass filtering. But then given that in most areas the filter resistor must be small (minimizing IR drops), one ends up adding considerable on-chip decoupling, which consumes very large silicon area.
Additionally for some ICs, a dedicated pin with an external good quality capacitor is either not affordable or available but shared with other sensitive analogue core functions that could suffer indirectly from the vary large ∂i/∂t flowing through the supply stray inductance.
In other prior art a high voltage NFET can be placed between the high voltage rail (VDH) and the gate to be charged. The gate of that switch would be controlled under the low voltage supply (VDL) that provides the charge to the gate. Because the NFET will choke as the gate voltage VG gets close to the low voltage supply (VDL), then end of charge is natural. The advantage of this approach is simple in design because the NFET is naturally cut off And there is no risk of overshooting the gate. However, when VDL is low (a few high voltage FET VTs is around 1 volt), the charge will be stopped too early. The gate would not make a full excursion to the VLD voltage. The control over the charge current profile is poor. It tends to be very close to the RC-type charge as shown in FIG. 8 with a relatively impulsive profile. To complete the gate charge excursion, a significant current still has to be drawn from the low voltage supply (VDL). And an additional tricky gate sensing circuit has to be added.
In the present disclosure, the charging current profile is better controlled and the voltage ripples caused by the charging current on the low voltage supply (VDL) is greatly depressed.